This invention relates generally to programmable logic devices, and more particularly to a method and system for developing and testing the functionality of an FPGA design.
Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacturer, and field programmable devices, which are programmable by the end user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electronically erasable programmable read only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD) devices, and programmable gate arrays (PISA).
As chip capacity continues to increase significantly, the use of field programmable gate arrays (FPGAs) is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized integrated circuit that is designed for a particular application and can be implemented as a specialized microprocessor. Notably, a FPGA is a programmable logic device (PLD) that has an extremely high density of electronic gates as compared to an ASIC. This high gate density has contributed immensely to the popularity of FPGAs. Notably, FPGAS can be designed using a variety of architectures that can include user configurable input/output blocks (IOBs), and programmable logic blocks having configurable interconnects and switching capability.
The advancement of computer chip technology has also resulted in the development of embedded processors and controllers. An embedded processor or controller can be a microprocessor or microcontroller circuitry that has been integrated into an electronic device as opposed to being built as a standalone module or xe2x80x9cplugin card.xe2x80x9d Advancement of FPGA technology has led to the development of FPGA-based system-on-chips (SoC) including FPGA-based embedded processor system-on-chips. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a microprocessor chip requires ancillary hardware electronic components to process instructions, a SoC would include all required ancillary electronics. For example, a SoC for a cellular telephone can include a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM. It should be understood within contemplation of the present invention that an FPGA-Based SoC does not necessarily include a microprocessor or microcontroller. For example, a SoC for a cellular telephone could also include an encoder, decoder, digital signal processor (DSP), RAM and ROM that rely on an external microprocessor. It should also be understood herein that xe2x80x9cFPGA-based embedded processor SoCsxe2x80x9d are a specific subset of FPGA-based SoCs that would include their own processors.
In order for device manufacturers to develop FPGA-based SoCs or FPGA-based embedded processor SoCs, it is necessary for them to acquire intellectual property rights for system components and/or related technologies that are utilized to create the FPGA-based SoCs. These system components and/or technologies are called cores or Intellectual Property (IP) cores. An electronic file containing system component information can typically be used to represent the core. A device manufacturer will generally acquire several cores that are integrated to fabricate the SoC.
Notwithstanding advantages provided by using FPGA-based SoCs, the development of these SoCs can be very challenging. Although a vast proportion of cores are commercially available, a significantly greater proportion of cores are proprietary. Proprietary cores can be called customer specific cores. Commercially available cores can typically include standardized interfaces, which can provide interconnectivity between system components from various vendors. Customer specific cores can typically include proprietary interfaces that do not readily facilitate interconnectivity between system components from other vendors. For example, customer specific cores can be written in proprietary languages, which are completely different from standardized languages. Since customer specific cores do not readily facilitate interconnectivity with other vendor""s system components, integrating customer specific cores during customization of an FPGA-based SoC can be time consuming. This resulted in increased development cost and greater time-to-market. Integration of the cores can include simulating, modeling and debugging the integrated cores in an operating environment. Simulation and modeling can be a daunting task since it can take hours if not days to simulate a few milliseconds of real time operation.
Importantly, verifying logic by probing the external pins has become increasingly difficult, if not impossible in certain scenarios. For example, flip-chip and ball grid array (BGA) packaging do not have exposed leads that can be physically probed using external tools such as an oscilloscope. Using traditional methods, capturing traces on devices running at system speeds in excess of 200MHz can be challenging. Furthermore, most circuit boards are small and have multiple layers with lines buried deep within layers of epoxy. These lines are inaccessible using an external tool. Notably, attaching headers to sockets or SoCs to aid in debugging can have adverse effects on system timing, especially in the case of a high-speed bus. Notably, attaching headers can consume valuable PCB real estate. The other difficulty is the fact that most functionality with the SoC is buried within the device and is not accessible via external pins. This inaccessibility leaves designers trying to debug internal logic without the ability to directly control or monitor this logic.
Given these and other inherent drawbacks, there is a need for a method and system for developing and testing the functionality of an FPGA SoC design.
The invention provides a method for automating the integration of the SoC system (as defined by an interactive processor system generator in accordance with the invention) and a SoC test and verification vehicle like Xilinx""s ChipScope logic analyzer. This invention allows users to specify the inclusion of a logic analyzer as well as the desired probe points for an FPGA based SoC as well as FPGA-based Embedded Processor SoCs. These signal probing selections are input by the user via a high level GUI. As users specify what hardware and software cores they want in their FPGA-based SoC via a system generator tool, they can also specify what internal signals they want to probe with an internal logic analyzer. The ChipScope logic analyzer, for example, can be downloaded into the FPGA along with the user""s SoC design to monitor internal signals. Currently, the user has to imbed the analyzer manually in the design. This is accomplished either by inserting it in the design source code (after the system generator tool has created it) or after an initial Place and Route (PAR) of the SoC design (which can greatly complicate the identification of, and access to the desired probe signals). In accordance with one aspect of the present invention, an appropriately sized logic analyzer would automatically be created and imbedded in the SoC design and the desired probe signals would be connected to the logic analyzer. In this manner, the debugging process is highly accelerated for an FPGA based SoC by making it easy for users to monitor signals. This technique provides two main advantages. The first is the aid to the user in the speedy debug of SoC designs. The second is the elimination of the need for source code by the user for the insertion of the logic analyzer which simplifies the user""s job and reduces the need for disclosing source code by the core vendors.
The method can include the step of executing software code for setting up and operating a logic analyzer located within the FPGA-based SoC. The software code can be the core software code for the logic analyzer. At least one monitor probe point within the FPGA-based SoCs can be defined for analysis by the logic analyzer. Information for the monitor probe point can be collected to facilitate analysis of signals while developing and verifying the FPGA-based SoC. The collecting step can further include the step of capturing electronic signal data for the monitor probe point. The capturing step can further include the step of capturing trace information for the monitor probe point and establishing triggers than can cause collection of trigger information for monitored probe points.
The method can further include the step of integrating the software code for the logic analyzer within the FPGA-based SoCs. The software code for the logic analyzer can alternatively be downloaded into the FPGA-based embedded processor SoCs.
In a further aspect of the invention, an integrated GUI with a processor system generator tool for development and verification of an FPGA-based embedded processor SoC is provided. The GUI can include a selection dialog for defining and selecting monitor probe points. The processor system generator tool would provide the necessary control/inputs/files to an integrated logic analyzer (ILA) setup as well as control software to minimize user work.
A prime example would be an output file that tells the logic analyzer what the signal set is, what triggers to set, and how to display it on a waveform window within a GUI display window. The selection dialog can further include an object for establishing trigger signals and conditions and/or an object for establishing trace parameters for the monitor probe points. The selection dialog can facilitate presentation of a selection attribute including, but not limited to, a target device family, a clock edge, a trigger type, a trigger match unit type, a number of trigger match units, a data depth, a data width, and a trigger width.